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Viterbi Encoder-Decoder

 
General Description

Viterbi decoding or convolutional decoding is a type of forward error correction algorithm. SeaSolve's High-perfornamce, low power Viterbi decoder VHDL IP is highly parameterizable and supports the parameters such as number of coded bits, traceback length, constraint length, number of soft decision bits, precision of branch metric accumulation, polynomial of each coded bits and puncturing rates. Viterbi decoders are usually implemented on XXXX. It provides a maximum throughput of more than XXX Mbits/s and consumes the least number of logic elements. It supports error correction for both continuous and burst errors. Versatile test bench is included with the viterbi decoder which lets the user to insert noise at any desired point.

Features
 
bullet Standards supported : DVB, 3G and IEEE 802.11 a/b/g
bullet Selectable code rates 1/2, 2/3, ¾
bullet Parameterizable trace backs depth of 35 to 105 for punctured data.
bullet Parameterizable constraint length up to 7
bullet Generator polynomials (G0 =1338,G1 = 1718)
bullet De puncturing of punctured convolutional encoded data
bullet Parameterizable generator polynomials
bullet Hard Decision Decoding
bullet Supports standards such as IEEE 802.11a/b/g and DVB
bullet VHDL simulation model
bullet Flexible architecture suitable for FPGA or ASIC
bullet Provide standard interface with external devices
 
Convolutional Encoder Block Diagram Viterbi Decoder Block Diagram
Licensing

For additional information and licensing of the IP core please Fill out this form